History of CCAL for E835 data taking -------------------------------------- Last Updated: 2/14/98 Things applicable to all runs:: ------------------------------- Dead blocks: R7W12 and R8W19. Not in the summers/trigger: R18W38. Blocks with double pulses: R13W25, R7W27, and R17W51 (which runs these started appearing is currently unknown.) Low gains in three blocks: R15W25, R13W25, and R7W27 (high gain constants.) Low hit multiplicity (ADC and TDC) in two blocks: R1W52 and R17W15 (hit multiplicity is as seen by online monitor, pulses are visibly smaller (with scope) than neighboring channels, calibration constants are near the average value - very possibly wrong due to a flaw in calibration method.) Noisy FERAs: vsn=29 (R8W1-16), vsn=44 (R11W49-64), vsn=62 (R16W17-32) Noisy defined as many channels in FERA with pedestals wider than 1 ADC count. Stack 1: Runs 533-550 ------------------------- Much debugging happened during this period, be careful using this data. Fera gate width set to 128 ns. TDCs read out with 160 ns offset and both leading and trailing edge.(**) Shaper thresholds set to 0.1V (~10mV pulse height). Dead/problem blocks: R8W20, R10W45, R18W17, R1W3, R18W38, R20W9, R8W19 and R7W12. 1. Swap in CCAL cabling present from before run 533 to sometime during run 538. R7W1-16 swapped with R8W1-16 at the FERA input. This is currently not corrected int the offline. 2. Many channels deemed "weak" meaning they had a low hit multiplicity (ADC), later discovered to be the result of loose FERA cards. 3. Shaper for R17W49-64 has a higher gain than the others, so the gain constants are 25% lower than the rest of the ring. Fixed prior to run 729. 4. Bad fera for R19W1-16 for runs 533-699. The pedestal means and widths were 0 for wedges 2,3,5,6,8 and 10, resulting in a low hit multiplicity for these channels. Stack 2: Runs 580-597 -------------------------- Dead/problem blocks: R8W20, R1W3, R18W38, R20W9, R8W19 and R7W12. 1. Weak channels mentioned above still present. 2. Shaper for R17W49-64 has a higher gain than the others, so the gain constants are lower than the rest of the ring. Fixed prior to run 729. 3. Bad fera for R19W1-16 for runs 533-699. The pedestal means and widths were 0 for wedges 2,3,5,6,8 and 10, resulting in a high adc threshold for these channels. Stack 3: Runs 688-714 -------------------------- Two dead blocks: R8W19 and R7W12. prior to the start of data taking: - All dead/problems blocks from stack2 now work except R8W19 and R7W12. - Shaper thresholds lowered to 0.8V (~8 mV pulse height). - Fera gate width shortened to 100 ns. - Timing work done on CCAL. - 24 ns added to CCAL offset in tdc registers (now = 184 ns)(**) 1. Bad fera for R19W1-16 for runs 533-699. The pedestal means and widths were 0 for wedges 2,3,5,6,8 and 10, resulting in a high adc threshold for these channels. 2. Shaper for R17W49-64 has a higher gain than the others, so the gain constants for these blocks are lower than those for the rest of the ring. Fixed prior to run 729. Stack 4: Runs 741-784 -------------------------- Two dead blocks: R8W19 and R7W12. prior to the start of data taking: - HV values adjusted to bring the gain constants for each tube to 2.6 MeV/ADC. - Offset changed to 0 in TDC registers and 184 ns of cable removed from the stop. (Effective TDC window remains the same, but no more lost hits.) - Shaper board mentioned above was repaired. (R17W49-64) 1. Problems with HV for runs 744-747. Affects channels R1-16W57. Stack 5-7: Runs 801-909 -------------------------- Two dead blocks: R8W19 and R7W12. prior to the start of data taking: - 8 ns of cable added to TDC stop. (Introduces noise from the FERA gate) 1. TDC channel for ring12 and wedge13 has strange behavior, all TDC info for this channel for runs 800-909 is ignored by the cluster timing routine. ********************** CHRISTMAS SHUTDOWN *************************** Stack 8-12: Runs 1005-1139 ---------------------------- Two dead blocks: R8W19 and R7W12. prior to the start of data taking: - 8 ns of cable removed from TDC stop. - Shaper thresholds lowered to 0.5V (~5mV pulse height). - Only leading edge of TDC data is recorded. - Noise from FERA gate still appears in TDCs. 1. Run 1005 was a special min bias run, and R1W49 was dead for this run. 2. Pedestals downloaded to FERAs for run 1005-1016 look suspicious for three FERAs (widths below 0.1 and means 2-3 adc counts too high.) 3. R8W48 died during run 1132. Stack 13-14: Runs1180-1215 --------------------------- Three dead blocks: R8W19, R7W12, R8W48. Stack 15: Runs1217-1257 --------------------------- Four dead blocks: R8W19, R7W12, R8W48, R4W3. Low gains in three blocks: R15W25, R13W25, and R7W27. Low hit multiplicity in two blocks: R1W52 and R17W15. 1. R4W3 dead for runs 1217-1270 due to bad shaper channel. Stack 16-19: Runs1271-1336 --------------------------- Three dead blocks: R8W19, R7W12, R8W48. Prior to data taking: - Shaper board for R4W1-16 replaced with spare. 1. R4W11 has low gain (gain constant 20% higher) and different shape for runs 1271-1340. (Problem with spare shaper board.) Stack 20: Runs1365-1396 ---------------------------- Three dead blocks: R8W19, R7W12, R8W48. Prior to data taking: - Problem with shaper for R4W11 repaired. 1. R3W1 has very few TDC hits for runs 1362-1372 (inclusive) due to a loose TDC cable. For these runs, the cluster timing routine ignores any TDC hits in this channel. Stack 21: Runs1400-1432 --------------------------- Three dead blocks: R8W19, R7W12, R8W48. 1. R2W26 has no ADC signal for runs 1400-1413 due to a bad solder joint in the FERA input card of the shaper board. TDC signal is fine. ********************** EASTER SHUTDOWN *************************** Stack 22-23: Runs2003-2049 --------------------------- Three dead blocks: R8W19, R7W12, R8W48. Stack 24: Runs2052-2060 --------------------------- Five dead blocks: R8W19, R7W12, R8W48, R7W29, R4W3. 1. R4W3 dead due to bad shaper channel, all runs this stack. 2. R7W29 dead due to a disconnected cable downstairs. 3. R4W17-24 have a low tdc multiplicity due to a bad TDC module. TDC hits in these channels are ignored by the cluster timing routine for runs 2052-2068. Stack 25: Runs2065-2078 --------------------------- Four dead blocks: R8W19, R7W12, R8W48, R7W29. Prior to data taking: - Problem shaper board replaced with spare (R4W1-16). 1. R7W29 dead due to a disconnected cable downstairs. 2. R4W17-24 have a low tdc multiplicity due to a bad TDC module, for runs 2065-2068 inclusive. TDC hits in these channels are ignored by the cluster timing routine for runs 2052-2068. Stack 26: Runs2086-2092 --------------------------- Four dead blocks: R8W19, R7W12, R8W48, R4W3. Prior to data taking: -Cable reconnected downstairs, R7W29 now works. 1. R6W7 had the wrong HV setting (512 V higher than normal) for run 2086-87. 2. R4W3 is dead in the shaper board for all runs this stack. Stack 27: Runs2098-2100 --------------------------- Three dead blocks: R8W19, R7W12, R8W48. Prior to data taking: - Problem shaper board repaired (R4W3). Stack 28-33: Runs2102-2157 --------------------------- Three dead blocks: R8W19, R7W12, R8W48. 1. R5W1 and R5W2 dead in ADC only for the first hour of run 2106. A loose connection was fixed at 13:16. Stack 34: Runs2162-2165 --------------------------- Four dead blocks: R8W19, R7W12, R8W48, R4W3. 1. R4W3 dead during entire stack due to dead shaper channel. Stack 35: Runs2175-2177 --------------------------- Three dead blocks: R8W19, R7W12, R8W48. Prior to data taking: - Problem shaper board repaired (R4W3). Stack 36-38: Runs2184-2203 --------------------------- Three dead blocks: R8W19, R7W12, R8W48. 1. R14W11 has a low hit multiplicity for runs 2184-2192. At 03:15 during run 2192, a loose fera card was reconnected. Note:: My logbook says that someone noticed this at 2189, but the data for the calibration traces it back to 2184. Stack39-46: Runs2218-2328 -------------------------- Three dead blocks: R8W19, R7W12, R8W48. Stack47: Runs2330-2341 -------------------------- Three dead blocks: R8W19, R7W12, R8W48. 1. R9W33-48 have a very large hit multiplicity for these runs, with the superfluous hits adc<5. This was found to be a fera whose pedestals fluctuated with time. This noisy FERA has existed all runs prior to this. Stack48: Runs2344-2357 -------------------------- Three dead blocks: R8W19, R7W12, R8W48. 1. Pedestals were taken before every run to handle problem from the previous stack. Stack49: Runs2359-2373 ------------------------- Three dead blocks: R8W19, R7W12, R8W48. Prior to data taking: -FERA mentioned above (vsn=35) was replaced. Stack50: Runs2376-2399 ------------------------- Three dead blocks: R8W19, R7W12, R8W48. 1. HV Mainframe5 turned itself off during run 2387 and during run 2393, what time during these runs will be investigated. Runs 2388 and 2394 were started after m5 was reset. Stack51-54: Runs2404-2441 ----------------------------- Three dead blocks: R8W19, R7W12, R8W48. Stack55: Runs2444-2460 ----------------------------- Three dead blocks: R8W19, R7W12, R8W48. 1. HV Mainframe3 turned itself off during run 2453 at 03:33, 97-07-06. (Run 2453 was stopped at 03:43.) Controller was replaced. Stack56-61: Runs3005-3099 ----------------------------- Three dead blocks: R8W19, R7W12, R8W48. Stack62: Runs3103-3128 ----------------------------- Three dead blocks: R8W19, R7W12, R8W48. Prior to data taking:: - FERA (vsn=9) replaced - HV Mainframe 2 controller replaced 1. HV Mainframe 2 controller replaced (swapped with a bad controller from M1) prior to run 3126 Stack63: Runs3136-3156 ----------------------------- Four dead blocks: R8W19, R7W12, R8W48, R4W3. Prior to data taking:: - HV Mainframe 2 controller replaced with working one 1. R4W3 dead entire stack due to dead shaper channel Stack64-65: Runs3162-3177 ----------------------------- Three dead blocks: R8W19, R7W12, R8W48. Prior to taking data:: - Shaper board in R4W1-16 replaced with spare Stack66-67: Runs3204-3233 ----------------------------- Four dead blocks: R8W19, R7W12, R8W48, R4W3. 1. R4W3 dead entire stack due to dead shaper channel Stack69-present: Runs3235-3346 ----------------------------- Three dead blocks: R8W19, R7W12, R8W48. Prior to taking data:: - Shaper board in R8W17-32 replaced with spare (spare has a dead channel corresponding to R8W19.) - Shaper board in R4W1-16 replaced with board removed from R8W17-32. - Discriminator threshold on R2W49-64 raised to read 0.7V on voltmeter since the previous setting (0.5V) corresponded to an ADC value lower than 5. (**) - Prior to run 741 the TDCs window was set using a width, a common stop (time determined by PBGOR strobe + delay) and an offset (time between the end of the window and the stop). It was discovered that any hits occuring after the window but before the stop occupied memory in the TDC. The maximum number of hits recorded is a parameter set in the initilization of the TDCs and determines the number of memory slots availible. Thus, if there were more hits than the maximum during the time window + offset, the earliest hits (the ones we are interested in) are overwritten by the later ones. THE POINT - If you are looking at this data, about 15% (rate dependent of course) of the blocks with adc counts above threshold have missing tdc information. Thus, an ontime pulse may have only a late TDC hit or no hits at all. Be careful with any cuts.